1. Technical Field
The present invention relates to a system and method for allocating test pattern instruction and data memory during test pattern generation. More particularly, the present invention relates to a system and method to pseudo-randomly allocate page table memory for test pattern instructions in order to produce complex test scenarios during processor execution.
2. Description of the Related Art
A processor test team typically employs test patterns to verify and validate a system design. Processor testing tools exist whose goal is to generate the most stressful test pattern for a processor. In theory, the generated test pattern should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test patterns.
Verifying and validating a processor using test patterns typically includes three stages, which are 1) test pattern build stage, 2) test pattern execution stage, and 3) validation and verification stage. During the test pattern build stage, a processor testing tool decides how to allocate memory for instructions and data that are included in the test patterns. This decision is critical due to the fact that memory allocation affects test coverage. As a result, the processor testing tool may allocate memory that, in turn, does not provide adequate test coverage.
The effects of this decision multiplies when the system includes a plurality of processors because memory may be allocated differently on each of the processors, thereby effecting the amount of coverage that the test patterns achieve.
What is needed, therefore, is a system and method that allocates page table memory for test pattern instructions and data in order to adequately test a processor system.